Dynamic Energy Quality Optimization through Reversible Adaptive Filtering in Reconfigurable Datapath Architectures

Abstract

Reconfigurable adaptive filter is a revolutionary reconfigurable data route architecture that is presented in this work with the purpose of resolving the ever-changing trade-off between energy quality and adaptive filtering that takes place. The four adaptive filtering techniques that reconfigurable adaptive selects dynamically are Least Mean Squares (LMS), Partial Update Normalized LMS (PU-NLMS), Set-Membership Normalized LMS (SM-NLMS), and Normalized LMS (NLMS). This selection is based on the grading difficulty levels that are present during runtime. The design places an emphasis on reusing modules, which results in a compact implementation of VLSI hardware that functions via the use of reversible logic techniques. As part of this study, we came up with a plan for an 8x8 multiplier circuit that uses a Feynman gate (FG) full adder along with a Press Gate (PG) design flow and can be turned around. This design resulted in a reduction in the depth of the multiplication module within the framework of a reconfigurable adaptive filter architecture. Synthesis assessments conducted by Xilinx have shown that this reversible design results in superior performance when compared to traditional architecture. There are several parts to a case study that looks at reconfigurable adaptive algorithms. These include an accurate resorting divider, a 5G input sequence with noise and the desired signal, and a link to the update control block of the LMS adaptive filter. The outcomes of synthesis research that compared two distinct multiplier designs on a Vertex-5 FPGA with four distinct filter algorithm levels gave information on power, latency, and area. In this study, it is shown how to use reconfigurable adaptive filters to get good adaptive filtering with changing energy quality using adaptive filters.